During reduced-data-rate (RDR) testing, a memory device, such as dynamic random-access memory (DRAM), is tested using low-speed test equipment. In particular, the data rate on a data (DQ) channel is reduced by repeating data bits in successive temporal bit positions. Then, a multiple pass test is performed using bit transitions in different bit positions during successive passes. This technique enables a full-interface test to be performed using low-speed test equipment.
Moreover, the ability to perform part or all of the production testing of the memory device using low-speed test equipment can facilitate high-volume, low-cost manufacturing. For example, many manufacturers have invested in test equipment that includes commodity memory interfaces, such as double data rate (DDR), and a low-speed test capability allows these manufacturers to leverage their existing test equipment.
RDR techniques typically rely on the ability to issue request commands during the low-speed testing. This is possible for many memory architectures, such as extreme data rate (XDR), because the command/address (CA) channel has a lower data rate than the DQ channel (for example, for XDR, the CA channel is 4-8× slower than the DQ channel). Consequently, when the data rate on the DQ channel is reduced, the CA channel continues to function properly.
However, many high-throughput memory architectures, such as XDR2 and the terabyte bandwidth initiative (TBI), use a high-speed fully differential CA channel that runs at the same speed as the DQ channel. Unfortunately, if RDR testing is performed on the CA channel in these high-throughput memory architectures, an invalid CA command will occur. Thus, RDR testing is currently not available for many high-throughput memory architectures.
Hence, there is a need for a device that supports communication of CA information during RDR testing without the above-described problems.
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